Complete ESP32-P4 Hardware Design Guide: Schematic, PCB Layout, Peripherals & Key Pitfalls to Avoid

ESP32-P4 is a high-performance RISC-V multimedia SoC launched by Espressif, featuring dual-core high-performance RISC-V processors + an independent low-power LP core. It integrates hardware H.264 encoding, MIPI-CSI camera interface, MIPI-DSI display interface, USB 2.0 OTG, Ethernet RMII, and a wide range of other peripherals. It is widely used in industrial HMI, edge vision, smart displays, robotics, medical equipment, and other applications.

When working on ESP32-P4 hardware development, many engineers can easily encounter issues related to power supply, crystal oscillator, high-speed MIPI signals, strapping pins, PSRAM/Flash power supply, and other areas. Based on Espressif’s official hardware design guidelines, this article provides a comprehensive overview of ESP32-P4 schematic design, PCB layout, peripheral circuits, common issues, and a hardware design checklist. It is suitable as a reference for hardware engineers during product-level design.

Note: New designs must use chip version v3.0 or later. Versions v1.0/v1.3 have differences in pin definitions and are not recommended for new projects.

1. Core Hardware Features of ESP32-P4

• Core: HP dual-core RISC-V up to 400 MHz; LP single-core RISC-V at 40 MHz, with an independent low-power system
• Memory: 768 KB HP L2MEM, 32 KB LP SRAM; supports on-chip / external PSRAM (16 MB/32 MB) and SPI Flash
• High-Speed Interfaces: MIPI-CSI (camera), MIPI-DSI (display), USB 2.0 OTG, RMII Ethernet, SDIO 3.0
• General-Purpose Peripherals: UART, I2C, SPI, ADC, touch sensors, and 55 GPIOs; all use 3.3 V I/O. 5 V input voltage is strictly prohibited
• Important: The ESP32-P4 chip itself does not include Wi-Fi/BLE. If wireless connectivity is required, an external Wi-Fi 6 / Bluetooth module (such as ESP32-C6) must be added.

2.Key Points for Schematic Design

2.1 Power Supply System Design

ESP32-P4 has multiple independent power domains, including HP, LP, IO, analog, and Flash/PSRAM power supplies. It cannot simply be powered by a single 3.3 V power rail.

1. Main Power Supply
   • The chip recommends a 3.3 V input, with peak current exceeding 380 mA. The DCDC power supply should provide sufficient current margin. It is not recommended to use an LDO directly to supply the chip’s main power.
   • Power pins include: VDD_HP, VDD_LP, VDD_BAT, VDD_ANA, multiple VDD_IO pins, VDD_FLASHIO, and VDD_PSRAM_0/1.
   • Place a 0.1 μF ceramic decoupling capacitor close to each power pin. Add a 10 μF capacitor at the main power input. The PSRAM/Flash IO power supply requires a combination of 0.1 μF + 1 μF capacitors, placed as close to the chip pads as possible.
2. Flash and PSRAM Power Supply
   • VDD_FLASHIO: Flash IO power supply, with a voltage range of 1.65–3.6 V;
   • VDD_PSRAM_0/1: PSRAM IO power supply, with a standard voltage of 1.8 V and a range of 1.65–1.95 V. It must have an independent voltage regulator and cannot be connected directly to 3.3 V. Otherwise, the PSRAM may malfunction, causing system crashes or corrupted data.
3. Analog Power Supply VDD_ANA
   • The analog power supply requires separate filtering. Place a 0.1 μF capacitor close to the pin and keep it as far away as possible from switching power supply noise.

Common mistake: Connecting the PSRAM IO directly to 3.3 V may cause the PSRAM to be unrecognized and result in system boot failure.

2.2 Clock Circuit

1. Main Crystal Oscillator (Required): 40 MHz, ±10 ppm accuracy. Crystal oscillators with other frequencies cannot be used. The firmware only supports a 40 MHz external crystal oscillator.
   • For the XTAL_P and XTAL_N pins, connect external load capacitors. Calculate the load capacitance according to the crystal oscillator datasheet and include PCB parasitic capacitance in the calculation. It is recommended to reserve positions for adjustable capacitors so they can be modified during later debugging.
2. RTC Crystal Oscillator (Optional): 32.768 kHz, used for RTC timing. It is recommended for low-power applications to improve sleep timing accuracy.

2.3 Flash & PSRAM Circuit

1. SPI Flash: A pull-up resistor is recommended for the CS pin. Reserve 0 Ω resistor positions on the SPI signal lines to facilitate signal timing adjustment and interference suppression during later debugging.
2. PSRAM: If Octal-SPI PSRAM is used, ensure that the IO voltage is strictly 1.8 V. Similarly, reserve 0 Ω resistors on the signal lines.
3. Place decoupling capacitors close to the power pins of all memory devices.

2.4 Strapping Boot Configuration Pins

Strapping pins determine the chip’s boot mode, such as Flash boot and download mode. These pins must be configured correctly in hardware and cannot be left floating. Floating pins may cause the chip to fail to boot normally or enter download mode incorrectly.

• Refer to Espressif’s official schematic and configure pull-up / pull-down resistors for the strapping pins;
• Do not arbitrarily reuse strapping pins as general-purpose GPIOs to avoid level interference during power-on that could affect the boot mode.

2.5 Reset Circuit

ESP32-P4 has a built-in reset function. An external reset IC can also be added if required. Pay attention to the logic level of the reset pin and do not incorrectly connect it to a high level, as this may prevent the chip from being reset properly.

2.6 High-Speed Peripheral Schematics

MIPI-CSI (Camera) / MIPI-DSI (Display)

• MIPI differential signals require an external REXT reference resistor. The resistor must be included in the schematic; otherwise, the MIPI interface will not work.
• CSI/DSI differential pairs should be designed as matched pairs in the schematic, and the PCB should strictly control the differential impedance to 100 Ω ±10%.

USB 2.0 OTG

• For the USB DP/DM pins, the v3.0 chip version adds a 1 MΩ pull-down resistor to the DP pin. Make sure it is configured according to the official schematic; otherwise, USB enumeration may fail and firmware cannot be downloaded.

RMII Ethernet

• The RMII clock is an input signal. If a 50 MHz clock output is required, the REF_50M_CLK_PAD pin should be used.
• Reserve series resistors on the RMII clock line for signal tuning.
• RMII pins can be remapped through software, so the pin mapping must be confirmed.

SDIO Interface

SDIO is used for TF cards. Pay attention to the power supply and voltage levels. The IO voltage is 3.3 V, and the signal traces should be routed with proper impedance control to avoid signal reflections.

3.PCB Layout Design

This chapter introduces the key points of how to design an ESP32-P4 PCB layout using an ESP32-P4 development board as an example.

Considering the communication quality of high-speed signal lines and potential interference with the RF module, please use at least a four-layer PCB design, as follows:

• Layer 1 (TOP): Signal traces and components.
• Layer 2 (GND): No signal traces here to ensure a complete GND plane.
• Layer 3 (POWER): Route power traces here. If possible, route high-speed signal traces here and ensure a complete reference plane.
• Layer 4 (BOTTOM): Route some signal traces here.

Power Supply

• Whenever possible, route the power traces on the inner layers (not the ground layer) and connect them to the chip pins through vias. Ensure the power traces are surrounded by ground copper.
• The trace width for the 3.3 V main power supply should be at least 25 mil.
• For the power traces of VDD_LP, VDD_IO_0, VDD_IO_4, VDD_IO_5, VDD_IO_6, VDD_BAT and VDD_ANA, use a trace width of at least 10 mil. Place a 10 µF capacitor at the power entry point for this series of power supply and a 0.1 µF capacitor for each power pin.
• The trace width for the main power supply traces of VDD_HP_0, VDD_HP_1, VDD_HP_2, and VDD_HP_3 should be at least 20 mil. Place a 10 µF capacitor at the power entry point for this series of power supply and a 0.1 µF capacitor for each power pin.
• For VDD_LDO and VDD_DCDCC, which handle higher current, use a trace width of at least 20 mil and place a 10 µF capacitor close to each power pin.
• It is recommended to use a star routing method to distribute power traces to each power pin.
• Because the VDD_HP power supply is by default fully controlled internally by ESP32-P4, the external DCDC should be placed close to the chip to ensure that the input, output, and feedback loops are as short as possible.

Crystal

Figure ESP32-P4 Crystal Layout shows a reference PCB layout of crystal design.

The layout of the crystal should follow the guidelines below:

• Ensure a complete GND plane for the crystal and chip.
• The crystal should be placed far from the clock pin to avoid interference on the chip. The gap should be at least 4.5 mm. It is good practice to add high-density ground vias stitching around the clock trace for better isolation.
• There should be no vias for the clock input and output traces.
• Components in series to the crystal trace should be placed close to the chip side.
• The external matching capacitors should be placed on the two sides of the crystal, preferably at the end of the clock trace, but not connected directly to the series components. This is to make sure the ground pad of the capacitor is close to that of the crystal.
• Do not route high-frequency digital signal traces under the crystal. It is recommended not to route any signal trace under the crystal. The vias on the power traces on both sides of the crystal clock trace should be placed as far away from the clock trace as possible, and the two sides of the clock trace should be surrounded by ground copper.
• As the crystal is a sensitive component, do not place any magnetic components nearby that may cause interference, for example large inductance component, and ensure that there is a complete large-area ground plane around the crystal.

USB

The USB layout should meet the following guidelines:

• Reserve space for resistors and capacitors on the USB traces close to ESP32-P4.
• Use differential pairs with a differential impedance of 90 Ω with a tolerance of ±10%. Use differential pairs and route them in parallel at equal lengths.
• USB differential traces should minimize via transitions as much as possible to ensure better impedance control and avoid signal reflections. If vias are necessary, add a pair of ground return vias at each transition point.
• Ensure there is a continuous reference layer (a ground layer is recommended) beneath the USB traces.
• Surround the USB traces with ground copper.

SDIO

The SDIO layout should follow the guidelines below:

• Minimize parasitic capacitance of SDIO traces as they involve high-speed signals.
• The trace lengths for SDIO_CMD and SDIO_DATA0 ~ SDIO_DATA3 should be within ±50 mil of the SDIO_CLK trace length. Use serpentine routing if necessary.
• For SDIO routing, maintain a 50 Ω single-ended impedance with a tolerance of ±10%.
• Keep the total trace length from SDIO GPIOs to the master SDIO interface as short as possible, ideally within 2000 mil.
• Ensure that SDIO traces do not cross layers. Besides, a reference plane (preferably a ground plane) must be placed beneath the traces, and continuity of the reference plane must be ensured.
• It is recommended to surround the SDIO_CLK trace with ground copper.
• For multi-layer PCB designs, it is recommended to route SDIO traces to an inner layer through vias immediately after being drawn out from the chip. This helps minimize interference with high-speed signal lines. Add a pair of ground return vias at each via transition point.

Touch Sensor

ESP32-P4 offers up to 14 capacitive IOs that detect changes in capacitance on touch sensors due to finger contact or proximity. The chip’s internal capacitance detection circuit features low noise and high sensitivity. It allows to use touch pads with smaller area to implement the touch detection function. You can also use the touch panel array to detect a larger area or more test points.

Figure ESP32-P4 Typical Touch Sensor Application depicts a typical touch sensor application.

To prevent capacitive coupling and other electrical interference to the sensitivity of the touch sensor system, the following factors should be taken into account.

Electrode Pattern

The proper size and shape of an electrode improves system sensitivity. Round, oval, or shapes similar to a human fingertip are commonly applied. Large size or irregular shape might lead to incorrect responses from nearby electrodes.

Figure ESP32-P4 Electrode Pattern Requirements shows the proper and improper size or shape of electrode. Please note that the examples illustrated in the figure are not of actual scale. It is suggested to use a human fingertip as reference.

PCB Layout

Figure ESP32-P4 Sensor Track Routing Requirements illustrates the general guidelines to routing traces. Specifically,

• The trace should be as short as possible and no longer than 300 mm.
• The trace width (W) can not be larger than 0.18 mm (7 mil).
• The alignment angle (R) should not be less than 90°.
• The trace-to-ground gap (S) should be in the range of 0.5 mm to 1 mm.
• The electrode diameter (D) should be in the range of 8 mm to 15 mm.
• Hatched ground should be added around the electrodes and traces.
• The traces should be isolated well and routed away from that of the antenna.

Waterproof and Proximity Sensing Design

ESP32-P4 touch sensor has a waterproof design and features proximity sensor function. Figure ESP32-P4 Waterproof and Proximity Sensing Design shows an example layout of a waterproof and proximity sensing design.

Note the following guidelines to better implement the waterproof and proximity sensing design:

• The recommended width of the shield electrode width is 2 cm.
• Employ a grid on the top layer with a trace width of 7 mil and a grid width of 45 mil (25% fill). The filled grid is connected to the driver shield signal.
• Employ a grid on the bottom layer with a trace width of 7 mil and a grid width of 70 mil (17% fill). The filled grid is connected to the driver shield signal.
• The protective sensor should be in a rectangle shape with curved edges and surround all other sensors.
• The recommended width of the protective sensor is 2 mm.
• The recommended gap between the protective sensor and shield sensor is 1 mm.
• The sensing distance of the proximity sensor is directly proportional to the area of the proximity sensor. However, increasing the sensing area will introduce more noise. Actual testing is needed for optimized performance.
• It is recommended that the shape of the proximity sensor is a closed loop. The recommended width is 1.5 mm.

4. Common Hardware Pitfalls

1. ❌ Connecting PSRAM IO directly to 3.3 V: PSRAM requires a 1.8 V power supply. Directly connecting it to 3.3 V will cause recognition failure and abnormal system startup.
2. ❌ Using a crystal oscillator other than 40 MHz: ESP32-P4 firmware only supports a 40 MHz external crystal oscillator. Other frequencies will not work.
3. ❌ Leaving Strapping pins floating: This can cause an incorrect chip boot mode and prevent the chip from booting from Flash.
4. ❌ No differential control or length matching for MIPI routing: This may cause camera image corruption, display flickering, or no display output.
5. ❌ Insufficient power supply current: The chip may reset or crash under heavy loads. The DCDC power supply must have sufficient current margin.
6. ❌ Using older v1.0/v1.3 chip versions for new projects: Their pin definitions differ from v3.0, and they have known hardware errata. New projects should prioritize v3.0 or later.
7. ❌ Applying 5 V input to GPIOs: All GPIOs are designed for 3.3 V logic levels. Applying 5 V input may damage the chip.

5. Hardware Design Checklist (Schematic + PCB)

Schematic Checklist

• Use chip version v3.0 or later
• Ensure all power domains are properly implemented, with PSRAM IO at 1.8 V
• Use a 40 MHz crystal oscillator; RTC crystal oscillator is optional
• Configure all Strapping pins correctly with no floating pins
• Ensure all Flash and PSRAM power decoupling capacitors are properly installed
• Ensure the MIPI REXT reference resistor is connected
• Configure the USB DP/DM resistors according to the v3.0 chip version
• Ensure all IOs use 3.3 V, with no direct 5 V input
• Ensure the reset circuit is correctly implemented

PCB Checklist

• Use a four-layer PCB stack-up with a complete GND reference plane
• Control MIPI differential impedance to 100 Ω, ensure intra-pair length matching, and provide ground shielding
• Place decoupling capacitors close to the chip pins and keep via connections short
• Keep the 40 MHz crystal oscillator away from high-speed signals
• Keep Flash/PSRAM traces as short as possible and reserve 0 Ω resistor positions
• Control USB differential impedance to 90 Ω and ensure length matching
• Do not route high-speed signals across split ground planes

Conclusion

As a high-performance multimedia RISC-V chip, ESP32-P4 presents its main hardware design challenges in multiple power domains, high-speed MIPI differential signals, PSRAM voltage, and Strapping pins. For product development, it is recommended to use chip version v3.0 or later, preferably with a four-layer PCB, while strictly following Espressif’s official hardware design guidelines.

Reserving debugging resistor positions in the schematic and implementing proper impedance and length matching control for high-speed signals on the PCB can significantly reduce the time and cost required for subsequent debugging